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Espressif Systems /ESP32-H2 /SPI1 /SPI_MEM_SUS_STATUS

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Interpret as SPI_MEM_SUS_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_FLASH_SUS)SPI_MEM_FLASH_SUS 0 (SPI_MEM_WAIT_PESR_CMD_2B)SPI_MEM_WAIT_PESR_CMD_2B 0 (SPI_MEM_FLASH_HPM_DLY_128)SPI_MEM_FLASH_HPM_DLY_128 0 (SPI_MEM_FLASH_RES_DLY_128)SPI_MEM_FLASH_RES_DLY_128 0 (SPI_MEM_FLASH_DP_DLY_128)SPI_MEM_FLASH_DP_DLY_128 0 (SPI_MEM_FLASH_PER_DLY_128)SPI_MEM_FLASH_PER_DLY_128 0 (SPI_MEM_FLASH_PES_DLY_128)SPI_MEM_FLASH_PES_DLY_128 0 (SPI_MEM_SPI0_LOCK_EN)SPI_MEM_SPI0_LOCK_EN 0 (SPI_MEM_FLASH_PESR_CMD_2B)SPI_MEM_FLASH_PESR_CMD_2B 0SPI_MEM_FLASH_PER_COMMAND

Description

SPI1 flash suspend status register

Fields

SPI_MEM_FLASH_SUS

The status of flash suspend, only used in SPI1.
SPI_MEM_WAIT_PESR_CMD_2B

1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
SPI_MEM_FLASH_HPM_DLY_128

1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
SPI_MEM_FLASH_RES_DLY_128

1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
SPI_MEM_FLASH_DP_DLY_128

1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
SPI_MEM_FLASH_PER_DLY_128

Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
SPI_MEM_FLASH_PES_DLY_128

Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
SPI_MEM_SPI0_LOCK_EN

1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
SPI_MEM_FLASH_PESR_CMD_2B

1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.
SPI_MEM_FLASH_PER_COMMAND

Program/Erase resume command.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data